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So solution is to wait in monitor (I have actually two - for input and output of DUT): forever For some reason, there is 100ps delay (which shouldn't be in behavioral simulation) in IDDR. I finally solved it - problem was in Xilinx unisim library.
#MODELSIM OVM HOW TO#
Any ideas what could be causing it or how to fix it? I use Modelsim 10.5 with resolution of 1ps. But new problem arisen – now monitor never sees EOF signal in 1 even though it is in 1 in wave several times. Since it's similar bug, I tried similar hack – I added #1ps right after dut_out_vi.clock) and it truly helped. If (dut_out_vi.eof = 1) // this never happens $display("DUT_OUT EOF: %b", dut_out_vi.eof) Tx = dut_out_transaction::type_id::create("tx") Now everything is correct in wave, but monitor sees wrong values (but only sometimes – usually with beginning of packet – valid signal changed from 0 to 1). But it created problem with output and monitor. I tried using "little hack": TMP_CLK INTERNAL_CLK, But internally, it takes previous value of data – for example previous value of CTL was 0, on rising edge it's 1, but DUT samples with rising edge that previous 0 as it didn't actualize inside modelsim. In Modelsim wave, this input (watching DUT input ports) is just fine. I generate transactions and send them to DUT using driver: forever It's a RGMII to internal interface converter (from DDR to SDR) using Xilinx UNISIM components to simulate special FPGA chip parts behavior. I have found that problem is in one specific component and created environment specifically for it. I am doing verification of VHDL component using OVM and ran into serious problems.